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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST059@linklings.com
SUMMARY:Plug-n-Play Testbench environment for ARM Coresight SoC-400
DESCRIPTION:Engineering Track Poster\n\nSowmya V M, Dhaval Panchal, Lalith
 raj Mailappa, Subramanian R, Naveen Srivastava, and Sekhar Dangudubiyyam (
 Samsung)\n\nThe Coresight architecture is an integral part of any processo
 r based design. ARM CoreSight architecture is a solution for debug and tra
 ce of complex SoCs. It provides a set of standard interfaces and programme
 r model views enabling partners to define CoreSight components and integra
 te them within the CoreSight architecture.  SOC DV efforts will be increas
 ed to setup the verification stimulus whenever the ARM architecture change
 s. Automated Verification testbench is one of the best solutions to ease t
 he DV efforts for Coresight related test sequences. This paper talks about
  generic parameterized automated SOC DV environment, which helps us in acc
 elerating the DV bring-up and reduce the time of verification cycle. The p
 lug-n-play testbench supports various ARM architecture base Coresight syst
 em. There is very minimal manual intervention and only a few user inputs a
 re required to implement the verification testbench for targeted SOC. The 
 testbench can be plugged in for verifying the debug data path in SoC desig
 n and to close the verification early than the project deadline.\n\nTopic:
  Back-End Design, Embedded Systems, Front-End Design, IP
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