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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST067@linklings.com
SUMMARY:Early Validation of Random TB using Formal Technology
DESCRIPTION:Engineering Track Poster\n\nEuibong Jung (Samsung)\n\nFunction
 al Coverage serves as a metric for measuring the completeness of verificat
 ion efforts, often requiring a significant time investment. The testbench 
 (TB) employed to achieve verification coverage may involve complex constra
 ints and incomplete scenarios, potentially causing issues of over-constrai
 nt or under-constraint due to its randomized nature. Such flawed or incomp
 lete random TBs can lead to unnecessary time and effort spent on checking 
 UNR or re-running regressions after a verification engineer's review. This
  paper presents a methodology for validating TBs under a simulation enviro
 nment using Formal Technology to mitigate the existing validation Turnarou
 nd Time (TAT). Leveraging Formal Technology and C2A(Constraint to Assume) 
 developed internally, constraint and coverage model in random simulation T
 B can be verified early to eliminate over/under-constraints. Furthermore, 
 additional functional coverage can be generated by applying internally dev
 eloped R2C(RTL to Coverage) and C2C(Counter to Coverage) to the RTL. As a 
 result, The improved TB can be applied to the simulator from the early sta
 ges, confirming a reduction in validation TAT. This approach facilitates t
 he creation of high-quality coverage-based TBs and helps the early detecti
 on of hard-to-find bugs in a simulator-based environment.\n\nTopic: Back-E
 nd Design, Embedded Systems, Front-End Design, IP
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