BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST068@linklings.com
SUMMARY:Peak Power Optimization using Active Datapath Operator Profiling
DESCRIPTION:Engineering Track Poster\n\nVijay Tayal, Sanchita Gupta, Amit 
 Dey, Anil Mishra, Hicham Anbar, Mohammad Saif Ansari, and Manish Kumar (Si
 emens)\n\nPower estimation has become a critical metric for design evaluat
 ion and thus the focus now is on both Average and Peak Power. Using strate
 gies like Clock-Gating, to reduce the average power may also reduce peak p
 ower. With focus on average power, the strategies which reduced peak power
  with no or minor impact on the average power are often not used. Neglecti
 ng high peak power can lead to increase in cost of packaging or even failu
 re. \n\nIn this paper, we propose peak power optimization technique by re-
 scheduling data path operators across cycles. Cycle Accurate Peak Power at
  RTL was used to identify the peak power region using RTL-PA tools e.g.  P
 owerPro. Waveform reconstruction using recon engine was used to generate a
 ctive operator profile for the identified region. Based on the knowledge o
 f active operators causing peak power, the RTL was hand modified and check
 ed for correctness using formal verification tools. The Cycle Accurate Pea
 k Power for the modified RTL was performed to validate the impact on Peak 
 Power.\n\nFrom the results it is clearly visible that same functionality o
 f RTL was achieved with lower peak power. There was no noticeable impact o
 n the average power of the design.\n\nTopic: Back-End Design, Embedded Sys
 tems, Front-End Design, IP
END:VEVENT
END:VCALENDAR