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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST103@linklings.com
SUMMARY:LINKED LIST PROOF ACCELERATOR
DESCRIPTION:Engineering Track Poster\n\nArjun Kumar (Broadcom)\n\nLinked l
 ists provide a flexible and efficient way to share resources across multip
 le queues. While implementing a linked list is straightforward, its verifi
 cation poses complexities. Using traditional simulation techniques, findin
 g and debugging can be challenging and time-consuming. Formal verification
  can accelerate this effort and enhance functional coverage. However, it i
 s limited by the scale at which it can operate. Linked List Proof Accelera
 tor is a generic and scalable solution that uses abstraction techniques to
  limit the state space and input parameterization for easy adoption. It en
 ables quicker debugging and left-shifts the bug-finding phase to the desig
 n phase.\n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
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