BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST109@linklings.com
SUMMARY:Autonomous Power Sequence validation solution for I/O using Solido
  Design Environment
DESCRIPTION:Engineering Track Poster\n\nravinder kumar (STMicroelectronics
 ) and Fouad Mkalech, Eric Mammi, and Vani Priya (Siemens)\n\nThe character
 ization of input/output (IO) devices is  complex and time-consuming proces
 s due to the multiple supplies involved, such as VDD and VDDE, which ramp 
 up at different rates and in different orders. This is particularly import
 ant in the context of modern complex IO design, which often require rigoro
 us validation to ensure reliable and robust operation.\n\nThis complexity 
 can be addressed with automation scripts that enable the efficient generat
 ion of various validation scenarios in characterization process. In this w
 ay, designers can save significant time and effort, while also improving t
 he accuracy and completeness of the validation process\n\nTo achieve this,
  the automation scripts is designed to automatically generate series of te
 sts that cover a range of supply ramp rates and orders. The scripts can be
  customized to the specific requirements of the IO device being characteri
 zed, and by addition to Solido Design Environment can incorporate a variet
 y of simulation and analysis techniques available, such as Monte Carlo ana
 lysis and sensitivity analysis.\n\nThe addition of an automation script fo
 r IO device characterization to the Solido Design Environment represents a
  significant technical advance in the design and verification of analog an
 d mixed-signal ICs, with important implications for efficiency, accuracy, 
 and reliability.\n\nTopic: Back-End Design, Embedded Systems, Front-End De
 sign, IP
END:VEVENT
END:VCALENDAR