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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST116@linklings.com
SUMMARY:An efficient QA methodology for SRAM libraries
DESCRIPTION:Engineering Track Poster\n\nHiroaki Koizumi and Shuji Katayama
  (Renesas Electronics) and Siddharth Ravikumar and Mary Rayburn (Siemens)\
 n\nAt Renesas, we develop compact and low-power SRAMs for our products. Fo
 r our SRAM library development, we produce and verify all 10,000+ memory i
 nstances generated by our Memory Compiler.  \n\nAll SRAM IPs must be valid
 ated across a wide range of process, voltage, and temperature (PVT) condit
 ions, as well as multiple views and formats for consistency and correctnes
 s, including logical, physical, timing, SPICE, and other views. This requi
 res significant time and effort.  \n\nTo enhance IP QA process in terms of
  efficiency and coverage, Renesas has built an SRAM IP QA methodology in c
 ollaboration with Siemens' Solido Crosscheck. This methodology includes se
 veral custom checks from Renesas, in addition to standard SRAM and IP chec
 ks. It covers all relevant front-end and back-end design views for IP prod
 uction and integration workflows, and enables Renesas to fully validate IP
 s in significantly less time than before. \n\nIn this paper, we will discu
 ss Renesas' efficient SRAM IP QA methodology. Within this methodology, we 
 will also highlight key QA checks for SRAM validation, the importance of s
 uch rules, and provide insight into QA efficiency and coverage of the flow
 .\n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
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