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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST124@linklings.com
SUMMARY:Scalable modeling of dynamic voltage compression on timing
DESCRIPTION:Engineering Track Poster\n\nTim Helvey (Marvell)\n\nOn leading
  node designs, we see power supply integrity becoming more important and m
 eeting the dynamic compression requirement becomes more difficult.  We can
  use various techniques to fix local hotspots, but these techniques can be
  time consuming and iterative.  Analyzing the power supply effect on timin
 g analysis can be computationally expensive.  To maintain schedule, we may
  need to leave some violations unfixed and model additional timing uncerta
 inty on instances which violate.  We used various techniques to model this
  and found only minor impacts.  By allowing a small number of violations t
 o be waived, we were able to improve the schedule.\n\nTopic: Back-End Desi
 gn, Embedded Systems, Front-End Design, IP
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