BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST127@linklings.com
SUMMARY:SSN and EMA Bus Path Automation
DESCRIPTION:Engineering Track Poster\n\nGreg Ford and Trinath Harikrishna 
 (Marvell)\n\nAs designs grow larger and more complex, more advanced Design
  for Test (DFT) approaches continue to be developed to keep up with the ca
 pacity required. One of these approaches is "Streaming Scan Network" (SSN)
 , which is aimed at distributing scan test data across the entire design t
 hrough a bus structure and allows for easy scalability with independent sc
 an channels in each block/core of the design. Another feature used as part
  of DFT is the "Early Margin Adjust" (EMA) capability of memory macros, wh
 ich allows for adjusting timing margins of the memory by setting register 
 values during test bring-up. Both functions require distribution to / thro
 ugh all hierarchical blocks in the design, which historically has been han
 dled manually, with the Physical Design team determining bus traversal pat
 hs through blocks and feeding that back to the DFT team for implementation
 . This approach can be extremely time consuming due to the complexities of
  chip floorplans introduced by rectilinear shapes and hierarchical block r
 euse, so is often deferred, risking late-breaking issues. This presentatio
 n details a set of systems designed to automate generation of paths throug
 h a design, providing access to optimized bus distribution orders for DFT 
 implementation, starting from the first floorplans.\n\nTopic: Back-End Des
 ign, Embedded Systems, Front-End Design, IP
END:VEVENT
END:VCALENDAR