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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
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UID:dac_DAC 2024_sess233_ETPOST134@linklings.com
SUMMARY:Accelerated Design Rule Learning for Silicon Photonics
DESCRIPTION:Engineering Track Poster\n\nApoorva Vakil, Romain Feuillette, 
 and Timothy Miller (GlobalFoundries)\n\nThe amount of data generated in 20
 25 is estimated to be 181 zettabytes (181,000,000,000,000,000,000,000 byte
 s). To accommodate this, the size of data centers keeps expanding, putting
  different servers of the same data center several miles away from each ot
 her. Optical fibers are a necessity between servers and leveraging Silicon
  Photonics comes into play. With only about 15 years of learning ("All-sil
 icon active and passive guided-wave components for λ = 1.3 and 1.6 µm": ht
 tps://ieeexplore.ieee.org/document/1073057), Silicon Photonics doesn't hav
 e as much legacy information as CMOS2 (~ 75 years: https://en.wikipedia.or
 g/wiki/History_of_the_transistor). We can't afford to wait another 50 year
 s, so how do we accelerate this learning pace? \n\nTo face this challenge,
  we will discuss strategies such as: anticipating design constraints based
  on FMEA analysis in order to accelerate design timeline, design compactio
 n to support higher packaging density, minimizing wafer scraps and improve
 ment of wafer yield.\n\nThis presentation will discuss our research approa
 ch, the hurdles we encountered and how we handled them as well as the curr
 ent limits and our future steps.\n\nFMEA: Failure Mode and Effect Analysis
 \n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
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