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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST136@linklings.com
SUMMARY:An Efficient Early Thermal Management Solution in 3DIC design
DESCRIPTION:Engineering Track Poster\n\nPing Ding, Guohua Zhou, and Keqing
  Ouyang (Sanechips Technology Co.,Ltd) and Li Zou and Shuqiang Zhang (Ansy
 s)\n\nMulti-die designs, 2.5DIC and 3DIC, have been rising in popularity i
 n last decade as they offer tremendously increased levels of integration, 
 smaller footprint, performance gains, and more. While they are attractive 
 for many applications, it also creates more stringent design bottlenecks i
 n the areas of thermal management and power delivery. For 3DICs, in additi
 on to the complex SoC/PCB interactions seen in their 2D counterparts, we m
 ust account for electrical and thermal coupling between dies as well.\n   
  For these advanced package design, such as 2.5D/3DIC, chiplets, power, th
 ermal, electromagnetics and mechanical – and their highly coupled interact
 ions – are the primary limiters of entitled performance, yield and cost. A
 s we know, when temperature increases, it increases the device leakage pow
 er consumption, and requires more cooling costs. Also, temperature increas
 e can have tremendous negative impact on the overall design performance, s
 uch as interconnect resistance hike, device performance degradation, and t
 he thermal induced noise can change the light wave phased in optical desig
 ns. \n    Higher thermal effects also cause reliability issues, like elect
 romigration failure, aging issue, and stress related failures. So thermal 
 management becomes very important to avoid thermal runaway and reliability
  issues. However, full 3DIC system thermal analysis with detail CTM takes 
 too much time at sign-off stage, and once thermal issues arise, there is n
 o space left to adjust on the SoC die. Therefore, in most cases, upgrading
  cooling equipment is almost the only option, and the cost is too high! We
  seek a shifting left method to manage chip thermal in the early stages. E
 arly thermal management can more efficiently avoid thermal run away, reduc
 e thermal management costs, and give designers more confidence during desi
 gn sign-off analysis.\n    Thermal aware floorplan & power plan with preli
 minary collateral in RedHawk-SC-Electrothermal at early stage can analyze 
 and predict power-thermal reliability issues, identify thermal issues earl
 y enables fixes/changes that can have a profound effect on reducing failur
 es with a minimum of design effort. Through early-stage thermal-stress ana
 lysis, we can avoid the warpage and solder joint reliability issues caused
  by thermal expansion. \nkeywords : 3DIC, thermal-aware floorplan, power-p
 lan, early-stage thermal management\n\nTopic: Back-End Design, Embedded Sy
 stems, Front-End Design, IP
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