BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST139@linklings.com
SUMMARY:DVD-aware STA and its silicon correlation results on 10nm test chi
 p
DESCRIPTION:Engineering Track Poster\n\nJongyoon Jung, Hyun-seung Seo, and
  Byunghyun Lee (Samsung) and Rajat Kukreja, Ajay Sahoo, Ji-Hun Kim, Dae-Hu
 n Jung, and Aniket Deshmukh (Cadence Design Systems, Inc.)\n\nAs technolog
 y scales down, metal resistances have increased, resulting in potentially 
 more voltage drop. Therefore, Dynamic Voltage Drop (DVD) significantly aff
 ects performance in recent process technologies. Moreover, transistor dens
 ity has increased, resulting in higher power density. Thus, power integrit
 y and timing check must be done simultaneously. In this work, DVD-aware ST
 A flow based on Cadence's Tempus PI is proposed. To show its effectiveness
  on real silicon, the proposed method is evaluated by correlating with 10n
 m test chip that is specially designed for DVD-aware STA and implemented i
 n Samsung's 10nm process.\n\nTopic: Back-End Design, Embedded Systems, Fro
 nt-End Design, IP
END:VEVENT
END:VCALENDAR