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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST140@linklings.com
SUMMARY:Row-Based Placement and Legalization for Mixed Signal Power Delive
 ry IP in Memory
DESCRIPTION:Engineering Track Poster\n\nJeongyoon Lee, Kyeongrok Jo, Seung
 hwan Lee, Seungkwang Hong, Heejin Bae, Jiwon Woo, Youngwook Kim, and Jungy
 un Choi (Samsung)\n\nThe turn-around-time for analog IP layout design sign
 ificantly exceeds that for digital, despite their low quantity. Although a
 utomated migration solutions for analog IP have been proposed recently, th
 eir practical application is still challenging because even when the schem
 atic is reused, layout reusability is often hindered by changes in design 
 rule, IP boundary, etc. In this work, we propose row-based placement and l
 egalization methodology, focusing on the mixed signal power delivery IP be
 cause 1) almost half of the analog circuit is occupied by power delivery I
 P quantitatively, 2) it is sensitive to parasitic RC rather than analog co
 nstraints such as matching. Precisely, it follows the steps, 1) schematic 
 analysis & component generation, 2) component matching with dynamic floorp
 lan adjustment, 3) global placement, 4) legalization for analog components
 , 5) vertical legalization with row power assignment, and 6) horizontal le
 galization with well bias alignment. Experimental results demonstrate that
  the proposed work can generate reasonable initial placement solutions wit
 hin 1 hour, with up to 150 components. The generated layouts have 4.05% ar
 ea overhead, 14.67% HPWL increase in average compared with the manual ones
 , which could be enhanced by the further optimization, either manually or 
 with additional algorithms.\n\nTopic: Back-End Design, Embedded Systems, F
 ront-End Design, IP
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