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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST142@linklings.com
SUMMARY:Architecture Area Evaluation Tool
DESCRIPTION:Engineering Track Poster\n\nAshishkumar Pal and Adarsh TR (Tex
 as Instruments (India) Pvt. Ltd.) and Kavithaa Rajagopalan (Eindhoven Univ
 ersity of Technology)\n\nAAET (Architecture Area Evaluation Tool) is desig
 ned to address the pressing need for accurate and unified area estimation 
 for future devices. A precise estimation plays an important role in determ
 ining the approximate cost of the devices in terms of area so as to meet t
 he market requirements.\n\nAAET aims in enabling seamless data consolidati
 on by efficiently processing information from various legacy devices, whic
 h can be configured based on frequency, memory, processor features etc. in
  order to adapt to the changing requirements of future devices.\n\nThe Das
 hboard provides a user-friendly and efficient tool for estimating area (sy
 nthesis and PD) using interactive GUI features, serving as a data analysis
  tool, with the goal of reducing workload, preventing manual errors, and f
 acilitating data-driven decision-making for competitive advantage.\n\nTopi
 c: Back-End Design, Embedded Systems, Front-End Design, IP
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