BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST151@linklings.com
SUMMARY:A Heuristic-Based Routing Methodology for Block-Level Memory Layou
 t Routability Enhancement
DESCRIPTION:Engineering Track Poster\n\nSichan Kim and Seunghwan Lee (Sams
 ung)\n\nAs the technology node shrinks, routing in memory devices is becom
 ing a challenging problem. Advanced commercial routing solutions have been
  introduced for dealing with more complex design rules and less routing re
 sources, however, routing results are still far from satisfactory. Complex
  routing patterns from those routing solutions are not meeting customer's 
 specific expectations, rather making it more difficult for engineers to ma
 nually modify it. In this paper we explore the possibility whether a simpl
 er approach, a heuristic-based routing methodology can be a better option 
 for improving routability. Our routing methodology simplifies entire routi
 ng process into two stages: global routing and local routing, and heuristi
 c-based algorithm is applied in each stage. With our routing methodology, 
 we could achieve higher routing success rate by on average 43%, with less 
 routing resource usage by on average 13% and less drc errors by on average
  68%.\n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
END:VEVENT
END:VCALENDAR