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DTSTAMP:20240626T180035Z
LOCATION:Level 2 Exhibit Hall
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UID:dac_DAC 2024_sess233_ETPOST154@linklings.com
SUMMARY:Matched Placement and Routing using Synchronized Unit Cell Array
DESCRIPTION:Engineering Track Poster\n\nPriyanka Madaan (NXP Semiconductor
 s); Akshita Bansal and Ashwani sanwal (Cadence Design Systems, Inc.); and 
 Avinash Tripathi (NXP Semiconductors)\n\nIn Analog Design, matching is ver
 y critical to ensure yield, as even a few millivolts difference between ne
 ighboring devices can break the circuit. In this paper, we present a flow 
 for matched placement and routing using Group Arrays. Group Arrays are rep
 eated pattern of synchronized unit cells. The unit cell is repeated in pat
 terns in the design such that the parameters (width, length etc.) of each 
 unit is same as that of others in the array. To create repeated design pat
 terns, number of rows and columns can be altered along with spacing betwee
 n cells and orientation pattern of the cells. Each unit cell comprises of 
 devices and routing, individually or in combination.  As Group Array suppo
 rts synchronous editing, changes made to unit cell is replicated across al
 l cells.  If the specifications are modified, then design changes can be d
 one very quickly by working on the unit cells, simplifying ECOs and DRC co
 rrections. The placement and routing of an entire block can be done effici
 ently using Group Array and is shown in this paper.\n\nTopic: Back-End Des
 ign, Embedded Systems, Front-End Design, IP
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