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DTSTAMP:20240626T180035Z
LOCATION:Level 2 Exhibit Hall
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UID:dac_DAC 2024_sess233_ETPOST157@linklings.com
SUMMARY:Design Methodologies for Minimizing Local Routing Congestions in L
 ow-level Metal Layers
DESCRIPTION:Engineering Track Poster\n\nDaeyeon Kim, HONGSEOK CHOI, Minkoo
 k Kim, and Sangyun Kim (Samsung)\n\nIn advanced technology node, the diffe
 rence in the ratio of cell height scaling and interconnect scaling has res
 ulted in local routing congestion in the low-level metal layers. This cong
 estion is one of the bottleneck factors in node scaling. In this paper, we
  address two approaches to alleviate the local routing congestion in the l
 ow-level metal layers: (1) increasing pin access points by utilizing the m
 iddle-of-line (MOL) layer as a pin of the standard cell, and (2) minimizin
 g local interconnections by merging repetitive logic combinations. We prop
 ose an efficient method for preparing the standard cells that offer routab
 ility gains, as well as equivalent cell swapping case by case that are exp
 ected to enhance routability during the placement and routing (P&R) stage.
  Our experiments show a 1.82% and 0.6% block area gain for MOL pin routing
  and merged logic cells, respectively. We demonstrate that alleviating loc
 al routing congestion in lower-level metal layers is an important key for 
 interconnect scaling.\n\nTopic: Back-End Design, Embedded Systems, Front-E
 nd Design, IP
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