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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST160@linklings.com
SUMMARY:GPU Accelerated Harmonic Balance SPICE Simulation
DESCRIPTION:Engineering Track Poster\n\nQikun Xue (NVIDIA) and Chen Zhao (
 Empyrean Technology)\n\nHarmonic balance (HB) simulation is a method to ca
 lculate frequency domain steady-state response in non-linear circuits. For
  multiple tones, high speed circuits in advanced Finfet process, the runti
 me of HB analysis becomes particularly challenging. And may often encounte
 r convergence issues for large netlists. In this paper, we proposed a new 
 method to accelerate the HB analysis by GPU acceleration. The runtime can 
 be reduced from 20 days down to 2 hours in a high speed LCVCO design in Fi
 nfet process while still meeting the accuracy requirements. It gives the c
 ircuit designer more flexibility to either run more circuit simulation bef
 ore tape-out or reduce the total SPICE simulation time.\n\nTopic: Back-End
  Design, Embedded Systems, Front-End Design, IP
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