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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST163@linklings.com
SUMMARY:AI-Enhanced Automated Optimization Workflow for HBM Interconnect o
 n Interposer
DESCRIPTION:Engineering Track Poster\n\nShineng Ma, Hao Hu, Bin Yu, and Ke
 qing Ouyang (Sanechips Technology Co.,Ltd) and Rodger Luo (Ansys)\n\nWith 
 the rise of generative AI applications, there is a growing demand for high
 -bandwidth memory in AI/GPU chips, and interposer designs like UCIE for D2
 D and SOC to HBM interconnects are increasingly popular for chiplets inter
 connection. Interposer designs face unique challenges like small trace wid
 th, high interconnect density, and the absence of a solid plane. These cha
 llenges make traditional SI flow time consuming and lack of silicon-based 
 material consideration. An efficient and accuracy pre-layout analysis flow
  is very urgently needed.\nThis paper proposes an efficient interposer hig
 h-speed design simulation and optimization flow. This flow is driven by op
 tiSLang, allowing for the configuration of design parameters and objective
 s. By leveraging various AI/ML algorithms, the solution space is explored 
 to identify the optimal design. This flow operates as a closed-loop automa
 tic iterative optimization process.\nIn summary, this paper presents an au
 tomated interposer pre-layout design simulation and optimization flow. The
  proposed flow enhances accuracy, speed, and realism compared to tradition
 al manual approaches, and the validation results demonstrate its effective
 ness and applicability.\n\nTopic: Back-End Design, Embedded Systems, Front
 -End Design, IP
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