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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST164@linklings.com
SUMMARY:Auto Grouping And Improvement Of IR Critical Regions Using Unsuper
 vised Learning
DESCRIPTION:Engineering Track Poster\n\nArpan Bhowmik, Abhishek Mahesh Chi
 nchani, Rishikanth Mekala, and Goda Ananth Somayaji (Samsung)\n\nIn our 2.
 5D/3D System on Chip (SoC) designs that are being developed at lower (< 10
 nm) technology nodes, it is crucial to ensure that the IR drop is within t
 he signoff threshold limits in order to achieve the targeted PPA goals. \n
 \nTraditionally this includes multiple iterations of IR simulations after 
 which the engineer identifies the IR, timing critical areas in the design 
 that need to be improved. Manual identification of even a handful of regio
 ns pose a significant bandwidth impact. \nUtilizing k-means clustering alg
 orithm, we have developed an end to end pipeline where the engineer can:\n
 \n•        Provide the IR threshold limit and the algorithm will provide t
 he list of regions where instances having drop higher than the threshold a
 re clustered.\n\n•        Provide the type of cell which is resistance cri
 tical and the algorithm will provide the list of regions where the instanc
 es of the specified cell type are clustered. (example: Level Shifters)\n\n
 •        Provide the Instance toggle rate data and algorithm will cluster 
 the regions based on use given high toggle rate threshold.\n\nThe regions 
 are provided in the form of bounding boxes which can then be incorporated 
 into the PnR flows like PG grid reinforcement, VT swap to downsize cells, 
 etc.\n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
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