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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST166@linklings.com
SUMMARY:RDL and Bump Automation for Early EMIR Analysis In 2.5D, 3D and Si
 ngle DIE Designs using RedHawk-SC Design ECO's
DESCRIPTION:Engineering Track Poster\n\nArpan Bhowmik, Raja Rama Chandra R
 ao, Rishikanth Mekala, and Goda Ananth Somayaji (Samsung)\n\nIn order to a
 chieve the targeted PPA goals in our Single Die/2.5D/3DIC designs, accurat
 e early analysis is crucial for IR and timing optimization from beginning 
 stage of the project. \n\nIn the beginning of the project cycle:\n\n•     
    RDL with BUMPs is not available, Full flat design hierarchy is not yet 
 available.\n\n•        Bump currents cannot be checked very early in desig
 n cycle and cannot be optimized.\n\n•        IA/IB weakness cannot be caug
 ht as power sources will be created on IB/IA pins for block level runs.\n\
 n•        RDL DEF + block runs will be taking more computational resources
 .\n\n•        For 3DIC designs, TSV model and Back metal resistances will 
 be missing in early EMIR analysis.\n\nOur approach is by utilizing Redhawk
 -SC EMIR Tool Design ECOs, we can draw RDL and BUMPs in our design. This m
 odified design with Virtual RDL and BUMPs is now used to perform IR and EM
  analysis. For 3DIC designs\n\n•        Accurate block level results by ac
 counting TSV, Back Metal resistances in block level runs. \n\n•        Mul
 tiple Design of Experiments can be performed.\n\n•        Accurate Top-Die
  results are available by accounting Bottom die parasitics for block level
  runs which helps in Top-Die design planning.\n\nModelling these additiona
 l challenges accurately is important for accurate early analysis.\n\nTopic
 : Back-End Design, Embedded Systems, Front-End Design, IP
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