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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST169@linklings.com
SUMMARY:Critical corners selection for standard cells LVF characterization
  using AI
DESCRIPTION:Engineering Track Poster\n\nAravind Radhakrishnan Nair (Infine
 on Technologies) and Ajay Kumar and Lars Kishchuk (Siemens)\n\nOn-chip var
 iation (OCV) is a significant factor affecting timing sign-off for digital
  designs at 20nm and below. At lower technology nodes, timing measurements
  such as propagation delay, setup time, and hold time may change by 50%-10
 0% due to statistical variation. In order to capture these variation effec
 ts accurately, timing .libs include variation modeling information defined
  by the Liberty Variation Format (LVF).\nLVF requires that each timing dat
 a point must also perform a statistical simulation/Monte Carlo analysis in
  order to capture the full distribution of behavior. Each data point is no
 t just a single additional table per timing arc. For each timing arc and n
 ominal measurement (e.g. delays, transitions and constraints), there are u
 p to 5 additional measurements used for statistical analysis: early and la
 te 3-sigma values, mean shift, standard deviation and skewness. This incre
 ases the runtime for SPICE characterization exponentially.\nIn this paper,
  we discuss a methodology for reducing SPICE characterization runtime by i
 dentifying the critical corners to characterize and generate the remaining
  LVF data using AI.\n\nTopic: Back-End Design, Embedded Systems, Front-End
  Design, IP
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