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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST170@linklings.com
SUMMARY:High Coverage QA for Process Variability Compensation in LVS Rule 
 Deck
DESCRIPTION:Engineering Track Poster\n\nHeejae Lim, Jaeyoung So, Minho Jun
 g, Jimin Yeo, Yunseong LEE, Bonhyuck Koo, and Yongseok Lee (Samsung) and A
 hmed Saleh and Mohamed Alimam (Siemens)\n\nManufacturing of semiconductor 
 designs pass through many complex steps, among which is process variabilit
 ies compensation that is applied to the layout geometries as selective edg
 e bias to improve the yield of the products. Biasing layout polygons will 
 impact the resistance and capacitances of the layout and thus the parasiti
 c extraction step needs to be aware of this bias values, moreover, the fin
 al polygons after bias must not result in a design rule violation and must
  not change the circuitry topology of the design. A biasing algorithm typi
 cally involves modifying the dimensions and/or positions of the polygons t
 o ensure that they meet the design rules and are manufacturable. Implement
 ing the bias algorithm correctly is critical to ensure correct compensatio
 n and manufacturability. This paper presents an automated QA method to ass
 ure bias is implemented correctly, thus ensuring downstream manufacturing 
 processes are applied to a correct layout. This solution introduces the LV
 S Retarget Checker designed for this purpose. The proposed method provides
  high coverage and enhancing the reliability of PDK (Process Design Kit), 
 and elevating the overall quality of the design.\n\nTopic: Back-End Design
 , Embedded Systems, Front-End Design, IP
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