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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST175@linklings.com
SUMMARY:An Automated Solution for Streamlining Qualifications of Connectiv
 ity and DRC Across Diverse 3DIC Packaging Technologies
DESCRIPTION:Engineering Track Poster\n\nTaehyung Lee, Woonggyu Lee, Minkyu
 ng Kim, Jihoon Park, Hyojin Kim, Changyoon Shin, Jiseon Lee, Yoojeong Yang
 , Seungjae Jung, and Jongkoo kang (Samsung) and Ahmed Saleh (Siemens)\n\nT
 he integration of multiple dies and substrates into a unified 3D-IC packag
 e presents a compelling solution to the limitations posed by scaling and c
 hallenges in SOC migration, making it a focal point in semiconductor advan
 cement. Despite its prominence, diverse fabrication methodologies, teams, 
 and formats introduce complexities to seamless integration. This approach 
 underscores the critical need for innovative approaches to ensure cohesive
  connectivity. Additionally, it emphasizes the imperative role of automati
 on in generating 3D-IC rule decks for swift and precise qualification. Eff
 icient qualification solutions demand automated systems capable of synthes
 izing rule decks while adhering to design specifications and manufacturing
  methods. This approach accelerates system netlist generation, layout asse
 mbly, and LVS (Layout vs. Schematic) rule deck creation, expediting physic
 al verification to mitigate challenges, and promote seamless integration a
 cross diverse substrates in semiconductor design and manufacturing.\n\nTop
 ic: Back-End Design, Embedded Systems, Front-End Design, IP
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