BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST181@linklings.com
SUMMARY:Machine Learning-based feasibility estimation of digital blocks fo
 r improved productivity in Analog-on-Top Back-End design flows
DESCRIPTION:Engineering Track Poster\n\nGabriele Faraone, Eugenio Serianni
 , Dario Licastro, Nicola DiCarolo, Michelangelo Grosso, and Giovanna Franc
 hino (STMicroelectronics)\n\nAnalog-on-Top Analog Mixed Signal (AMS) Integ
 rated Circuit (IC) design is a time-consuming process predominantly carrie
 d out by hand. Within this flow, usually, some area is reserved by the top
 -level integrator for the placement of digital blocks. Specific features o
 f the area, such as size and shape, have a relevant impact on the possibil
 ity of implementing the digital logic with the required functionality. We 
 propose an automated evaluation methodology to predict the feasibility of 
 digital implementation based on a set of high-level features avoiding time
 -consuming Place-and-Route trials so to provide fast feedback between Digi
 tal and Analog Back-End designers during top-level placement.\n\nTopic: Ba
 ck-End Design, Embedded Systems, Front-End Design, IP
END:VEVENT
END:VCALENDAR