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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST190@linklings.com
SUMMARY:Dashboard Model for Foundry Early Node Assessments using Synopsys 
 Design.da
DESCRIPTION:Engineering Track Poster\n\nLuna Kang, Jayson Seo, Ann-Woo Lee
 , and James Ban (Synopsys)\n\nWith the increasing complexity and size redu
 ction of System-on-Chips (SoCs), evaluating diverse design rules becomes c
 rucial in early-stage Design-Technology Co-Optimization (DTCO) and initial
  Performance, Power, and Area (PPA) assessments. \nIn response to these ch
 allenges, this paper presents a novel approach for detecting workflows at 
 early nodes, specifically tailored for Samsung Foundry. This task is relat
 ively straightforward for experienced engineers but poses challenges for b
 eginners, leading to time-consuming and error-prone processes. \nThis inno
 vative workflow leverages DesignDash, an advanced data visualization and m
 achine intelligence-based design optimization solution by Synopsys. Design
 Dash facilitates efficient data collection and visualization. \nThe propos
 ed early node DTCO/PPA workflow focuses on problem detection, outlining ke
 y parameters to assess when conducting an evaluation. In the initial stage
 s of Foundry projects, various issues can arise in design kits (DK), techn
 ology files, libraries, and enablement tools, such as Fusion Compiler (FC)
 . Addressing these challenges swiftly is imperative to shorten the schedul
 e required for PPA forecasting. \nThe workflow enables engineers to assess
  the feasibility of library cells and implementation flows through floor-p
 lanning, placement and routing analysis. By consolidating checklist items 
 and providing actionable insights, this approach enhances visibility and s
 ignificantly reduces turnaround time. \nTo further streamline the process,
  a customized interface is integrated into the existing DesignDash framewo
 rk, empowering users to swiftly identify and address issues. \nThis paper 
 not only presents an optimized workflow for early node DTCO/PPA but also e
 mphasizes the importance of knowledge sharing, encouraging the exchange of
  success stories.\n\nTopic: Back-End Design, Embedded Systems, Front-End D
 esign, IP
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