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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST193@linklings.com
SUMMARY:A Solution for Optimizing Customerized-MMB
DESCRIPTION:Engineering Track Poster\n\nFeilong Pan, Minqiang Peng, Keqing
  Ouyang, and Guohua Zhou (Sanechips Technology Co.,Ltd) and Fengfeng Tang 
 (Synopsys)\n\nAs the proportion of memories increasing in design, MMB (Mul
 ti-Memory Bus) interface is widely used in HPC core for memory test, which
  is a predefined bus in Function RTL, providing an access to multiple memo
 ry arrays and no need for memory wrappers. As a result of MMB interface ap
 plication, the test area, timing impact and routing congestion can be redu
 ced. However, there are some challenges when using MMB interface. The memo
 ries inside MMB interface only support serially test which means test time
 , test cost and the chip time-to-market will increase. \nIn this paper, we
  propose some solution for above challenges. \nThe memory subgroups of one
  MMB interface will be tested parallelly, and the outputs of every two adj
 acent subgroups will make a comparison in-situ. In order to ensure the ass
 uracy of the compare results, the output data of one subgroup will also fe
 ed into processor for comparation. \nThe repair logic is also shared betwe
 en the parallel test subgroups. A common repair solution will be applied f
 or the test groups.\n\nTopic: Back-End Design, Embedded Systems, Front-End
  Design, IP
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