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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST199@linklings.com
SUMMARY:Accelerating IO Liberty Generation through ML based Solution
DESCRIPTION:Engineering Track Poster\n\nPawan Verma, Anil-kumar Dwivedi, a
 nd Saurabh Srivastava (STMicroelectronics) and Ajay Kumar and Wei-Lii Tan 
 (Siemens)\n\nTime-to-market is a crucial factor in today's competitive chi
 p design landscape. Accurate timing and power analysis are essential for s
 uccessful tapeout, demanding fast and precise Liberty characterization dat
 a (.libs). Traditional methods, heavily reliant on SPICE simulations, are 
 often time-consuming and resource intensive. This presentation investigate
 s the application of AI to revolutionize library characterization in two d
 ifferent chip design scenarios.\n\nScenario 1 leverages ML to analyze exis
 ting PVT data and build accurate models for timing, power, and noise acros
 s various Liberty formats (NLDM, CCS, CCSN and LVF). This dramatically red
 uces characterization time for new PVT additions, offering up to a 100x ru
 ntime savings. Importantly, the generated .libs maintain high accuracy, wi
 th deviations from Spice simulations within 5% for timing & 10% for leakag
 e power and internal power energy.\n\nScenario 2 optimizes the characteriz
 ation flow by identifying a critical subset of .libs from existing librari
 es and generating the remaining .libs within a target accuracy range. This
  significantly reduces the need for recharacterization, saving over 50% of
  time and resources during Spice model updates or minor design changes.\n\
 nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
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