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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST202@linklings.com
SUMMARY:Solving the antenna debug challenge in physical design verificatio
 n
DESCRIPTION:Engineering Track Poster\n\nRahul Sai T Govindaswamy (Google),
  Nermeen Hossam and Anish Padhi (Siemens), Karishma Qureshi (Google), Gurp
 reet Lamba (Siemens), and Rakesh reddy Katukuri (Google)\n\nDesign teams f
 ind it increasingly challenging to debug antenna violations, especially at
 \nadvanced nodes, due to increasing complexity in antenna rules. Antenna r
 ule checks may\ncontain multiple scenarios with different conditional cons
 tructs, which make it difficult\nfor engineers not only to distinguish whi
 ch equation has been used for calculating the\nfailure, but also how to fi
 x the issue. They typically rely on multiple runs or a trial-and-\nerror m
 ethod to fix the antenna violations, both of which are inefficient, time-c
 onsuming\nsolutions.\n\nWe present an innovative antenna debugging flow th
 at calculates the exact number of\ndiodes that should be added to fix ante
 nna errors in a single run. Given the required diode\narea that should be 
 added to fix an antenna violation, as well as the option to categorize\nvi
 olations by net, designers can now resolve antenna errors accurately and e
 fficiently.\n\nTopic: Back-End Design, Embedded Systems, Front-End Design,
  IP
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