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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST205@linklings.com
SUMMARY:Physical Design With Intelligence
DESCRIPTION:Engineering Track Poster\n\nBindu Rao, Jagadeesh Gnanasekaran,
  Prasenjit Ray, Sai Prashant, Anand Kumaraswamy, Srinivas Jammula, and Raj
  Dua (Intel Corporation)\n\nOptimizing chip Power, Performance, Area, Sche
 dule, and Cost (PPASC) is crucial to stay competitive in today's rapidly e
 volving technological landscape. Optimal design PPASC, require designers t
 o explore large design space of functional, physical and process parameter
 s that have complex relationships amongst themselves and optimize designs 
 for conflicting goals iteratively. The quality of results is highly depend
 ent on engineering expertise and limited by schedule and cost priorities. 
 AI techniques can augment physical design and optimization effort with cap
 abilities for multi-objective design exploration, replace traditional iter
 ative feedback cycles with data driven insights and automate manual tasks 
 with pattern recognition capabilities. The use of AI in backend design can
  enhance efficiency, quality, reliability and have higher chance of reachi
 ng PPASC minima as compared to conventional methods. \nIn this talk we wil
 l discuss some of the application of AI in physical design for clock param
 eter tuning, place and route recipe generation, last mile PPASC optimizati
 on, design robustness analysis and design rule fixing and share preliminar
 y results from design testcases. Results indicate measurable benefit in te
 rms of PPASC, design quality and reliability. It also streamlines design p
 rocess, ensure execution predictability and free-ups engineering resource 
 for higher value tasks paving way for innovative, reliable, and improved P
 PASC chips that can shape the future of technology.\n\nTopic: Back-End Des
 ign, Embedded Systems, Front-End Design, IP
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