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BEGIN:VEVENT
DTSTAMP:20240626T180035Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST206@linklings.com
SUMMARY:Heterogeneous 3DIC  Multi Voltage Timing Signoff
DESCRIPTION:Engineering Track Poster\n\nTusharkant Mishra, Ranjith V R, an
 d Damodaran Trikkadeeri (Samsung) and Santosh Varanasi (Synopsys)\n\nCross
  die paths in 3DIC requires many additional signoff corner analysis compar
 ed to conventional 2DIC     signoff corners owing to different possible co
 nditions at each die level. In case of multi voltage 3DIC interface, signo
 ff corners need to be coupled with 3DIC voltage scenarios in order to crea
 te complete multi voltage signoff scenarios. 3DIC simultaneous multi volta
 ge analysis compresses the voltage scenarios per unique 3DIC process/temp/
 BEOL combinations, which in turn reduces no. of analysis corners and helps
  in reducing compute requirement. Dominant corner selection approach helps
  further limit the analysis corners and reduce the overall compute require
 ment. Context derived from 3DIC multi voltage timing   analysis can be use
 d as voltage scenario specific I/O budget (min/max) to die level 2DIC Timi
 ng analysis in order to optimize the setup/hold timing of 3DIC    interfac
 e \nConfigurable delay cells added on 3DIC interface paths can be used for
  silicon tuning of 3DIC interface     paths\n\nTopic: Back-End Design, Emb
 edded Systems, Front-End Design, IP
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