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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST208@linklings.com
SUMMARY:A New Approach to Efficient Prelim Package Generation for Faster S
 OC Implementation
DESCRIPTION:Engineering Track Poster\n\nBhupendra Singh, Shoikat Das, Saur
 abh Srivastava, and Anil Dwivedi (STMicroelectronics)\n\nIn the fast-paced
  semiconductor world, rapid time-to-market is crucial. Traditional SoC dev
 elopment, waiting for fully developed IPs, hinders speed and competitivene
 ss. This presentation introduces the concept of preliminary IP CAD views, 
 generated as soon as IP specifications are defined. This allows SoC develo
 pers to start design (flow setup and cleanup) and provide feedback earlier
 , significantly reducing overall cycle time. We propose an optimized appro
 ach for generating these preliminary views, achieving up to 40% faster run
 time and minimizing delays caused by human intervention. This streamlined 
 technique allows for faster iterations and feedback, increasing developmen
 t speed and competitiveness in the competitive industry.\n\nTopic: Back-En
 d Design, Embedded Systems, Front-End Design, IP
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