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BEGIN:VEVENT
DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST212@linklings.com
SUMMARY:Avoiding CDC bugs introduced during Synthesis Optimizations and Ne
 tlist Transformations
DESCRIPTION:Engineering Track Poster\n\nsuresh barla and PARAS MAL JAIN (S
 ynopsys), harish Aepala and anshul bansal (Meta), and Gunjan Mamania and K
 enneth Trejos (Synopsys)\n\nDesign synthesis flows are not aware of Clock 
 Domain Crossing (CDC). Thus, synthesis optimizations that are built to enh
 ance power, performance, and area (PPA), may cause corruption in CDC paths
  and therefore, the netlist generated by the synthesis tools can introduce
  new CDC errors even after CDC signoff at the RTL. \n\nThe synthesis optim
 izations may also cause functional glitch issues due to retiming, self-gat
 ing, and mux-decompositions which can result in silicon escapes.\nCurrentl
 y, designers use ad hoc methods such as manual synthesis constraints, full
  CDC re-verification at gate-level, or relying on Gate-level Simulation (G
 LS) to overcome these challenges. However, it is error prone due to over-c
 onstraining, high noise-level during re-verification, or low GLS coverage.
  \n\nUsing VC SpyGlass CDC-aware Fusion Compiler flow, correct-by-construc
 tion synthesis is performed with regard to avoiding CDC bugs during netlis
 t transformation.\nRunning this automated flow using the following steps:\
 n•        After RTL CDC signoff using VC SpyGlass CDC, a Static database i
 s generated to guide the synthesis\n•        Fusion Compiler generates syn
 thesis constraints using the Static database to ensure no corruption happe
 ns to CDC paths and no functional glitches are introduced\n\nIntegrating t
 his technology in the flow mitigates the risk of introducing any new CDC v
 iolations in Netlist that were previously qualified at RTL.\n\nTopic: Back
 -End Design, Embedded Systems, Front-End Design, IP
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