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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST216@linklings.com
SUMMARY:Coverage-based FV signoff – The complete cleanup methodology
DESCRIPTION:Engineering Track Poster\n\nGilboa Alin, Daher Kaiss, Anmol Pa
 tel, Aarti Gupta, and Gavriel Gavrielov (Intel Corporation)\n\nFormal-Veri
 fication (FV) is aiming to become a mainstream validation flow. For that, 
 a signoff methodology is needed in the same way there is for dynamic valid
 ation. The main potential issues in FV are: overconstraint by assumptions,
  and assertions that don't cover the whole design. FV tools are able to cr
 eate automatic cover points and verify that they are reachable and checked
  by at least one assertion. The number of cover points can reach hundreds 
 of thousands and many of them can be unreachable or unchecked. The problem
  is with resolving this multitude methodology violations. Cleaning the sim
 ple ones using pattern matching can reduce the numbers a lot, but there ca
 n be many others part of which are real issues. Therefore, it is important
  to strive to reach 0 violations. We present a breakthrough methodology th
 at helps cleaning both reachability and checker violations efficiently. Us
 ing these methods, the number of remaining violations can approach zero in
  a few days. In the presentation we show how the flow has been successfull
 y applied to some projects and helped reveal both overconstraints and miss
 ing quality checkers.\n\nTopic: Back-End Design, Embedded Systems, Front-E
 nd Design, IP
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