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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST223@linklings.com
SUMMARY:Automated Constraint Promotion Methodology from IP to SoC for Comp
 lex Designs
DESCRIPTION:Engineering Track Poster\n\nMallik Devulapalli and Rimpy Chugh
  (Synopsys)\n\nIP cores require integration into top-level subsystems and/
 or SoCs. Writing constraints manually for top level design is prone to err
 ors and difficult to verify and manage. This Synopsys webinar will cover h
 ow automated SDC constraints promotion from the IP to SoC level provides h
 igh-quality SDC relative to traditional manual time-consuming approaches. 
 We will demonstrate the approach taken and benefits observed using automat
 ed constraints promotion and generation on an early PCIeŽ Gen 6 design res
 ulting in shorter TAT and improved PPA. Lastly, we will illustrate how des
 igners can ensure constraints correctness is maintained or bettered during
  the constraints promotion effort\n\nTopic: Back-End Design, Embedded Syst
 ems, Front-End Design, IP
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