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DTSTAMP:20240626T180035Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST224@linklings.com
SUMMARY:Advanced Static Methodology for Complete Connectivity and Glitch S
 ignoff
DESCRIPTION:Engineering Track Poster\n\nAbhishek Ghate (HCL Technologies) 
 and Saurav Choudhary and Vikas Sachdeva (Real Intent)\n\nA chip design con
 sists of interconnected blocks providing advanced functionality. While the
 se blocks are thoroughly verified, the integrity of connections between th
 ese pre-verified components lacks clear ownership and efficient verificati
 on processes. With growing design complexity, the number of such connectio
 ns can reach millions and lead to unexpected problems, which may appear la
 te in the design flow. Therefore, a robust methodology for early checking 
 of connection integrity at the RTL and netlist level is crucial. Current f
 ormal, simulation, and script-based approaches for connectivity checking f
 ace challenges, such as a lack of key functionality, scalability limitatio
 ns, debugging difficulties, and inefficient usability.\n\nIn contrast, thi
 s paper introduces a novel static approach to defining a comprehensive set
  of rules at both the block and top-level, addressing issues such as the e
 limination of improper connectivity that may lead to block abutment issues
  during physical design, clock domain identification for specific instance
  ports, detection of driven pins within a module and ensuring glitch-free 
 input pins for specified instances. We successfully verified connectivity 
 and glitches on an active SoC design with this methodology in a matter of 
 days, as opposed to weeks of work with alternative methods.\n\nTopic: Back
 -End Design, Embedded Systems, Front-End Design, IP
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