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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_FED108@linklings.com
SUMMARY:A Novel Automation flow to generate SV-UVM Testbench with integrat
 ed BFMs
DESCRIPTION:Engineering Track Poster\n\nParthasarathy Ramesh, Sagar Jogur,
  Raminder Kaur, and Atul Lele (Texas Instruments)\n\nThe design verificati
 on (DV) phase in chip production lifecycle is a crucial and time-consuming
  process.\nFor any new IP/SoC, creating a DV environment from scratch is t
 ime consuming, repetitive and cumbersome task. This usually requires 2-3 w
 eeks of effort from DV Engineer. Furthermore, if third party VIPs are requ
 ired, it takes more time to figure out the configurations needed for the s
 ame and sometimes takes unnecessary debug sessions.\nThis paper presents a
  newly developed automation flow which takes inputs from the user on requi
 red BFMs (in house or third-party) and generates a testbench with all the 
 UVM components in it. These include, the TB top, UVM-Env, UVM agents, scor
 eboard etc. The BFMs are picked from a common location which can be made a
 ccessible to all the DV work areas. The BFMs are instantiated here with kn
 own config sets and user need only give minimal information to the automat
 ion flow.\nAs of today, this flow has been implemented for IPDV. It can be
  extended to be used on SOC DV in future.\n\nTopic: Back-End Design, Embed
 ded Systems, Front-End Design, IP
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