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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20240625T180000
DTEND;TZID=America/Los_Angeles:20240625T190000
UID:dac_DAC 2024_sess236_RESEARCH113@linklings.com
SUMMARY:Reset Domain Crossing Design Verification Closure using Advanced D
 ata Analytics Techniques
DESCRIPTION:Work-in-Progress Poster\n\nREETIKA REETIKA and Sulabh Khare (S
 iemens)\n\nThe modern SoCs are equipped with complex reset architectures t
 o meet the low-power and high-performance requirements.  Multiple reset do
 mains in a design can cause reset domain crossing (RDC) issues when data f
 rom one asynchronous source reset domain propagates to either a different 
 asynchronous, synchronous, or no-reset destination domain.  The data gener
 ated by the RDC verification tools is very large, consisting millions of R
 DC paths.  The analysis of this data is a very time consuming and challeng
 ing task for the design and verification engineers, that often involves ma
 ny iterations.  In this paper we will highlight how we can automate the RD
 C results analysis using data processing and data analytics techniques to 
 provide faster RDC verification closure.\n\nTopic: AI, Autonomous Systems,
  Cloud, Design, EDA, Embedded Systems, IP, Security
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