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DTSTAMP:20240626T180034Z
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UID:dac_DAC 2024_sess236_RESEARCH1737@linklings.com
SUMMARY:Representation-Independent Resubstitution for Area-Oriented Logic 
 Optimization
DESCRIPTION:Work-in-Progress Poster\n\nAndrea Costamagna and Alessandro Te
 mpia Calvino (École Polytechnique Fédérale de Lausanne); Alan Mishchenko (
 University of California, Berkeley); Satrajit Chatterjee (Kepler AI); and 
 Siang-Yun Lee and Giovanni De Micheli (École Polytechnique Fédérale de Lau
 sanne)\n\nLogic synthesis is a design phase that relies on heuristic algor
 ithms to optimize graph representations of digital circuits. The choice of
  a graph representation depends on target technology, design properties, a
 nd desired optimization metrics. While logic synthesis heuristics follow g
 eneral principles, their realization often entails high engineering costs 
 due to tight dependencies on specific circuit representations. This paper 
 proposes a representation-independent algorithm for area-oriented optimiza
 tion to transcend representation-specific tweaks and enhance adaptability 
 across diverse technologies and designs. The experimental results show tha
 t our method can achieve additional average improvements of up to 9.74% co
 mpared to state-of-the-art representation-dependent engines.\n\nTopic: AI,
  Autonomous Systems, Cloud, Design, EDA, Embedded Systems, IP, Security
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