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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20240625T180000
DTEND;TZID=America/Los_Angeles:20240625T190000
UID:dac_DAC 2024_sess236_RESEARCH1769@linklings.com
SUMMARY:A High-Throughput, Energy-Efficient, and Constant-Time In-SRAM AES
  Engine with Massively-Parallel Bit-Serial Execution
DESCRIPTION:Work-in-Progress Poster\n\nAndrew Dervay and Wenfeng Zhao (Bin
 ghamton University)\n\nThis paper presents a high-throughput, energy-effic
 ient, and constant-time in-SRAM Advanced Encryption Standard (AES) engine.
  The proposed in-memory AES ensures high-throughput operation exploiting t
 he column-wise single instruction multiple data (SIMD) processing of compa
 ct round functions for both electronic-codebook (ECB) and counter (CTR) mo
 des of operation. Moreover, we proposed a processor-assisted key loading s
 trategy and a prudent memory management scheme to minimize the memory foot
 print needed for AES to improve the peak operating frequency and energy ef
 ficiency of the underlying compute SRAM hardware. The bit-serial processin
 g further guarantees the constant-time execution of AES, providing strong 
 resistance to side-channel timing attacks. Experimental results show that 
 our proposed AES ECB design achieves 2.4×(149×) throughput, 2.4×(270×) thr
 oughput per area, 2.3×(7.7×) per block energy improvement as compared to t
 he state-of-the-art non-constant-time (constant-time) designs, respectivel
 y. The resulted AES Counter (CTR) mode design achieves 1.9× per block ener
 gy improvement as compared to the state-of-the-art reconfigurable IMC AES 
 CTR designs.\n\nTopic: AI, Autonomous Systems, Cloud, Design, EDA, Embedde
 d Systems, IP, Security
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