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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20240625T180000
DTEND;TZID=America/Los_Angeles:20240625T190000
UID:dac_DAC 2024_sess236_RESEARCH2082@linklings.com
SUMMARY:A General Purpose IMC Architecture with ADC-Awared Neural Networks
DESCRIPTION:Work-in-Progress Poster\n\nMin-Gwon Song, Shin-Uk Kang, and Mi
 n-Seong Choo (Hanyang University)\n\nIn analog or mixed-signal in-memory c
 omputing (IMC) applications, the focus is typically on the bit cell, parti
 cularly during the inference period. However, for transmitting multiplicat
 ion-and-accumulation (MAC) results to subsequent layers, IMC macros must c
 onvert analog signals into digital domain using analog-to-digital converte
 rs (ADCs), often the most power and area-intensive components in IMC syste
 ms. Addressing this, we present an efficient training/inferencing algorith
 m tailored for specific IMC applications, introducing an ADC-less IMC macr
 o design suitable for practical memory systems. This novel architecture el
 iminates the need for power-intensive ADCs, opting for reconfigurable conv
 entional memory structures with sense amplifiers, like DRAM or SRAM arrays
 . This study introduces an algorithm that integrates sense amplifiers into
  both the training and inference processes without extra hardware additive
 s.\n\nTopic: AI, Autonomous Systems, Cloud, Design, EDA, Embedded Systems,
  IP, Security
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