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DTSTAMP:20240626T180034Z
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UID:dac_DAC 2024_sess236_RESEARCH417@linklings.com
SUMMARY:A Parallel-trial Double-update Annealing Algorithm for Enabling Hi
 ghly-effective State Transition on Annealing Processors
DESCRIPTION:Work-in-Progress Poster\n\nAkira Hyodo, Satoru Jimbo, Daiki Ok
 onogi, Genta Inoue, Thiem Chu, Masato Motomura, and Kazushi Kawamura (Toky
 o Institute of Technology)\n\nAnnealing processors have attracted attentio
 n as domain-specific computers to solve combinatorial optimization problem
 s (COPs) efficiently. Furthermore, their performance can be enhanced by th
 e merge method that enables updating multi-variables simultaneously. Howev
 er, directly implementing the merge method on an annealing processor requi
 res large-scale computational and memory resources.\nIn this paper, we pro
 pose a parallel-trial double-update annealing (PDA) algorithm that integra
 tes the merge method into the annealing computation flow. Also, we can rea
 lize its processor by a minor extension to the existing near-memory archit
 ecture. Simulation results for several COPs demonstrate that PDA can find 
 higher quality solutions than the conventional annealing algorithm.\n\nTop
 ic: AI, Autonomous Systems, Cloud, Design, EDA, Embedded Systems, IP, Secu
 rity
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