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DTSTAMP:20240626T180033Z
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UID:dac_DAC 2024_sess236_RESEARCH983@linklings.com
SUMMARY:AiDAC: A Low-Cost In-Memory Computing Architecture with All-Analog
  Multibit Compute and Interconnect
DESCRIPTION:Work-in-Progress Poster\n\nZihao Xuan, Song Chen, and Kang Yi 
 (University of Science and Technology of China)\n\nAnalog in-memory comput
 ing (AiMC) is an emerging technology that shows fantastic performance supe
 riority for neural network acceleration. However, as the computational bit
 -width and scale increase, high-precision data conversion and long-distanc
 e data routing will result in unacceptable energy and latency overheads in
  the AiMC system. In this work, we focus on the potential of in-charge com
 puting and in-time interconnection and show an innovative AiMC architectur
 e, named AiDAC, with three key contributions: (1) AiDAC enhances multibit 
 computing efficiency and reduces data conversion times by grouping capacit
 ors technology; (2) AiDAC first adopts row drivers and column time accumul
 ators to achieve large-scale AiMC arrays integration while minimizing the 
 energy cost of data movements. (3) AiDAC is the first work to support larg
 e-scale all-analog multibit vector-matrix multiplication (VMM) operations.
  The evaluation shows that AiDAC maintains high-precision calculation (les
 s than 0.79% total computing error) while also possessing excellent perfor
 mance features, such as high parallelism (up to 26.2TOPS), low latency (<2
 0ns/VMM), and high energy efficiency (123.8TOPS/W), for 8bits VMM with 102
 4 input channels.\n\nTopic: AI, Autonomous Systems, Cloud, Design, EDA, Em
 bedded Systems, IP, Security
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