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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Lobby
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UID:dac_DAC 2024_sess237_RESEARCH1137@linklings.com
SUMMARY:Accelerating Heterogeneous Workloads Using A Reconfigurable In-Mem
 ory Computing Architecture
DESCRIPTION:Work-in-Progress Poster\n\nYanfeng Yang, Yi Zou, Yiyang Lin, X
 ianfeng Song, and Yingbo Hao (South China University of Technology)\n\nAs 
 a small effort towards general purpose CIM paradigm, in this paper, we pro
 pose a heterogeneous workloads centric compute-in-memory (HWCCIM) architec
 ture. Particularly, we present a design to compile essential algorithmic o
 perations into an address table for in-memory computing circuits. Leveragi
 ng a reconfigurable address generation unit to guide data movement within 
 different in-memory computing-based operator arrays, it is able to complet
 e calculations and producing corresponding results. We further illustrate 
 the construction of HWCCIM architecture in a behavioral-level circuit mode
 l. We also evaluate the proposed architecture using two classical algorith
 ms, the Fast Fourier Transform (FFT) and the Multilayer Perceptron (MLP) a
 lgorithms. Compared to conventional approaches, HWCCIM achieves a maximum 
 latency acceleration of 1.5x and an average latency acceleration of 1.3x.\
 n\nTopic: AI, Autonomous Systems, Cloud, Design, EDA, Embedded Systems, IP
 , Security
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