BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180034Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20240626T180000
DTEND;TZID=America/Los_Angeles:20240626T190000
UID:dac_DAC 2024_sess237_RESEARCH1201@linklings.com
SUMMARY:Efficient Prediction of SRAM Read Access Time and Yield via Neural
  Network Leveraging Transfer Learning and Transformer Models
DESCRIPTION:Work-in-Progress Poster\n\nSungho Park, Jaehyeon Moon, Giseok 
 Kim, Dohyung Kim, Seong-Ook Jung, and Bumsub Ham (Yonsei University) and H
 anwool Jeong (Kwangwoon University)\n\nWe propose neural network models th
 at predict read access time (RAT) and read access yield (RAY) in SRAM, con
 sidering wide range of design variables. Using transfer learning, the RAT 
 model reduces post-layout simulation time and training costs, achieving 1.
 2 million times faster prediction time of 0.18ms than HSPICE, with 2.14% e
 rror rate. The RAY model leverages transformer architecture for enhancing 
 accuracy with 11k times faster prediction time of 0.27s than HSPICE, with 
 1.31% error rate. Both models save time for entire design process and enha
 nce accuracy, with considering macro-level interactions and employing regu
 larization methods specifically designed to effectively capture nonlineari
 ties.\n\nTopic: AI, Autonomous Systems, Cloud, Design, EDA, Embedded Syste
 ms, IP, Security
END:VEVENT
END:VCALENDAR