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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20240626T180000
DTEND;TZID=America/Los_Angeles:20240626T190000
UID:dac_DAC 2024_sess237_RESEARCH1712@linklings.com
SUMMARY:Enhancing Delay-driven LUT Mapping with Boolean Decomposition
DESCRIPTION:Work-in-Progress Poster\n\nAlessandro Tempia Calvino and Giova
 nni De Micheli (École Polytechnique Fédérale de Lausanne) and Alan Mishche
 nko and Robert Brayton (University of California, Berkeley)\n\nAshenhurst-
 Curtis decomposition (ACD) is a known decomposition technique used, in par
 ticular, to map combinational logic into LUT structures when synthesizing 
 hardware designs. However, available implementations of ACD suffer from ex
 cessive complexity and slow run time, which limits their applicability and
  scalability. This paper presents several simplifications leading to a fas
 t and versatile technique of ACD suitable for delay optimization. We utili
 ze this new formulation to enhance delay-driven LUT mapping by performing 
 ACD on the fly. Compared to state-of-the-art technology mapping, experimen
 ts demonstrate an average delay improvement of 17.94%, with affordable run
  time. Additionally, our method improves heavily optimized LUT networks.\n
 \nTopic: AI, Autonomous Systems, Cloud, Design, EDA, Embedded Systems, IP,
  Security
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