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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20240626T180000
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UID:dac_DAC 2024_sess237_RESEARCH507@linklings.com
SUMMARY:GL0AM: GPU Logic Simulation Using 0-Delay and Re-simulation Accele
 ration Method
DESCRIPTION:Work-in-Progress Poster\n\nYanqing Zhang, Haoxing Ren, and Bru
 cek Khailany (NVIDIA)\n\nWe present GL0AM, a GPU-accelerated logic simulat
 or that performs delay-annotated gate-level simulation, supporting a wide 
 range of sequential gate types and simulation scenarios, including SRAMs. 
 We propose a methodology to perform the simulation in 2 portions to increa
 se parallelism in the application, where the first portion performs 0-dela
 y cycle-simulation, and the second performs re-simulation. We use netlist 
 graph partitioning to minimize synchronization overhead during the 0-delay
  simulation to increase speedup for this difficult to parallelize simulati
 on process. GL0AM achieves simulation speedup of 15-448X when compared to 
 a commercial simulator across a diverse set of benchmarks, which we aim to
  open-source.\n\nTopic: AI, Autonomous Systems, Cloud, Design, EDA, Embedd
 ed Systems, IP, Security
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