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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20240626T180000
DTEND;TZID=America/Los_Angeles:20240626T190000
UID:dac_DAC 2024_sess237_RESEARCH572@linklings.com
SUMMARY:mROB: Multi-Level ReOrder Buffer Design with Reduced Area and Powe
 r
DESCRIPTION:Work-in-Progress Poster\n\nSai Praneeth Madduri, Mingxuan He, 
 Fangping Liu, and Sang Wook Do (Futurewei Technologies)\n\nRe-Order Buffer
  (ROB) is a fundamental component in modern microprocessor designs. A nove
 l design is proposed to significantly reduce the area and dynamic power of
  a conventional ROB design without performance loss. A novel hardware stru
 cture removes redundancies existing in the original ROB entries by storing
  common information shared by many such entries separately. Cycle-accurate
  simulation results show that the area and power are reduced by 47% and 39
 % respectively in a CPU configuration modelled after the Intel Skylake pro
 cessor. A design methodology is proposed for the\nnovel design considering
  a trade-off between performance and power/area with a quantitative approa
 ch.\n\nTopic: AI, Autonomous Systems, Cloud, Design, EDA, Embedded Systems
 , IP, Security
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