BEGIN:VCALENDAR VERSION:2.0 PRODID:Linklings LLC BEGIN:VTIMEZONE TZID:America/Los_Angeles X-LIC-LOCATION:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20240626T180002Z LOCATION:Level 2 Lobby DTSTART;TZID=America/Los_Angeles:20240626T180000 DTEND;TZID=America/Los_Angeles:20240626T190000 UID:dac_DAC 2024_sess256@linklings.com SUMMARY:Late Breaking Results Posters DESCRIPTION:Late Breaking Results Poster\n\nLate Breaking Results: A real- time diffusion-based filter for human pose estimation on edge devices\n\nH uman Pose Estimation (HPE) is increasingly being adopted in a wide range o f applications, from healthcare to Industry 5.0. To address the intrinsic inaccuracy of such CNN-based software, the current trend involves applying filtering models to refine and improve the inference results. However, st ate...\n\n\nChiara Bozzini, Michele Boldo, Enrico Martini, and Nicola Bomb ieri (University of Verona)\n---------------------\nLate Breaking Results: Evaluation of Human Action Quality with Linear Recurrent Units and Graph Attention Networks on Embedded Systems.\n\nRecent evolutions of recurrent neural networks (RNN) such as S4, S4D, and LRU, have shown remarkable pote ntial for very long-range sequence modeling tasks for vision, language, an d audio. They have shown a capacity to capture dependencies over tens of t housands of steps. Unlike transformers, which f...\n\n\nFilippo Ziche and Nicola Bombieri (University of Verona)\n---------------------\nLate Breaki ng Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Inte gration (mLSI)\n\nControl channels on microfluidic large-scale integration (mLSI) chips are prone to blockage and leakage defects. The state-of-the- art test methods suffer efficiency concerns. In this work, we propose a bu ilt-in self-test (BIST) method that drastically improves the test efficien cy. Given n to-be-test...\n\n\nMengchu Li (Technical University Munich); H anchen Gu (Swiss Federal Institute of Technology Zurich); Yushen Zhang (Te chnical University Munich); Siyuan Liang (The Chinese University of Hong K ong); Hudson Gasvoda, Rana Altay, and Emre Araci (Santa Clara University); Tsun-Ming Tseng (Technical University Munich); Tsung-Yi Ho (The Chinese U niversity of Hong Kong); and Ulf Schlichtmann (Technical University Munich )\n---------------------\nLate Breaking Results: Majority-Inverter Graph M inimization by Design Space Exploration\n\nThe majority-inverter graph (MI G) is a homogeneous logic network widely used in logic synthesis for major ity-based emerging technologies. Many logic optimization algorithms have b een proposed for MIGs, including rewriting, resubstitution, and graph mapp ing. However, unlike AIGs, research on optimiza...\n\n\nSiang-Yun Lee and Alessandro Tempia Calvino (École Polytechnique Fédérale de Lausanne); Hein z Riener (Cadence Design Systems, Inc.); and Giovanni De Micheli (École Po lytechnique Fédérale de Lausanne)\n---------------------\nLate Breaking Re sults: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region Constraints\n\nField-programmable gate array (FPGA) macr o placement holds a crucial role within the FPGA physical design flow sinc e it substantially influences the subsequent stages of cell placement and routing. In this paper, we propose an effective and efficient routability- driven macro placement algorithm for ...\n\n\nHao Gu, Jian Gu, Keyu Peng, Jun Yang, and Ziran Zhu (Southeast University)\n---------------------\nLat e Breaking Results: TriSC: Low-Cost Design of Trigonometric Functions with Quasi Stochastic Computing\n\nLow-cost and hardware-efficient design of t rigonometric functions is challenging. Stochastic computing (SC), an emerg ing computing model processing random bit-streams, offers promising soluti ons for this challenge. The existing implementations, however, often overl ook the importance of the data conv...\n\n\nSercan Aygun, Mehran Shoushtar i Moghadam, and M. Hassan Najafi (University of Louisiana at Lafayette)\n- --------------------\nLate Breaking Results: Circuit-Algorithm Co-design f or Learnable Audio Analog Front-End\n\nThis paper presents a circuit-algor ithm co-design framework for learnable audio analog front-end (AFE) which includes an analog filterbank for feature extraction and a classifier base d on Depthwise Separable Convolutional Neural Network (DSCNN). Instead of the traditional approach to design the anal...\n\n\nJinhai Hu and Zhongyi Zhang (Nanyang Technological University), Cong Sheng Leow (University of M ichigan), Wang Ling Goh (Nanyang Technological University), and Yuan Gao ( Institute of Microelectronics)\n---------------------\nLate Breaking Resul ts: Extracting QNNs from NISQ Computers via Ensemble Learning\n\nThe recen t success of Quantum Neural Networks (QNNs) prompts model extraction attac ks on cloud platforms, even under black-box constraints. These attacks rep eatedly query the victim QNN with malicious inputs. However, existing extr action attacks tailored for classical models yield local substitute Q...\n \n\nZhenxiao Fu and Fan Chen (Indiana University, Bloomington)\n---------- -----------\nLate Breaking Results: Differential and Massively Parallel Sa mpling of SAT Formulas\n\nDiverse solutions to the Boolean satisfiability (SAT) problem are essential for thorough testing and verification of softw are and hardware designs, ensuring reliability and applicability to real-w orld scenarios. We introduce a novel differentiable sampling method, calle d DiffSampler, which employs g...\n\n\nArash Ardakani, Minwoo Kang, Kevin He, Vighnesh Iyer, Suhong Moon, and John Wawrzynek (University of Californ ia, Berkeley)\n---------------------\nLate Breaking Results: On the One-Ke y Premise of Logic Locking\n\nThe evaluation of logic locking methods has long been predicated on an implicit assumption that only the correct key c an unveil the true functionality of a protected circuit. Consequently, a l ocking technique is deemed secure if it resists a good array of attacks ai med at finding this correct key. I...\n\n\nYinghua Hu, Hari Cherupalli, Mi ke Borza, and Deepak Sherlekar (Synopsys)\n---------------------\nMixed-Ce ll-Height Detailed Placement under Multi-Cell Spacing Constraints\n\nAs te chnology scales down, multi-cell spacing constraints are imposed by modern circuit designs. In this paper, we propose a detailed placement algorithm considering multi-cell spacing constraints. First, an SAT-based multi-cel l spacing violation reduction method is presented to reduce the number of. ..\n\n\nBenchao Zhu (Fudan University), Zheng Zeng (Fuzhou University), an d Jianli Chen (Fudan University)\n---------------------\nLate Breaking Res ult: AQFP-aware Binary Neural Network Architecture Search\n\nAdiabatic Qua ntum-Flux-Parametron (AQFP) is a superconducting logic with extremely high energy efficiency. Recent research has made initial strides toward develo ping an AQFP-based crossbar accelerator. However several critical challeng es from both the hardware and software side remain, preventing th...\n\n\n Zhengang Li (Northe), Xuan Shen (Northeastern University), Geng Yuan (Univ ersity of Georgia), Maoud Zabihi (Northeastern University), Tomoharu Yamau chi (Tokyo City University), Yanzhi Wang (Northeastern University), and Ol ivia Chen (Tokyo City University)\n---------------------\nLate Breaking Re sults: Modern Automatic PCB Placement with Complex Constraints\n\nExisting printed circuit board (PCB) placement often fails to address complex cons traints (e.g., diverse wire widths and intricate spacing rules) arising fr om heterogeneous components in modern designs. Manual placement requires e xpertise and is time-consuming. Thus, automated PCB placement is desir...\ n\n\nChien-Hao Tsou, Sheng-Yah Lin, Wei-Chen Hung, and Yao-Wen Chang (Nati onal Taiwan University)\n---------------------\nLate Breaking Results: LLM -assisted Automated Incremental Proof Generation for Hardware Verification \n\nIn this paper, we propose a methodology for hardware verification assi sted by Large Language Models (LLMs) in the incremental proof generation p rocess. First, an LLM identifies the basic module of the Design Under Veri fication (DUV), followed by expanding the proof scope as more modules are added. L...\n\n\nKhushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Cha ndan Kumar Jha, and Rolf Drechsler (University of Bremen)\n--------------- ------\nLate Breaking Results: Machine Learning Based Reference Ripple Er ror Suppression in Successive Approximation Register Analog-to-Digital Con verters\n\nThis work presents a machine learning (ML) technique to suppres s reference ripple errors in successive approximation register (SAR) analo g-to-digital converter (ADC). Reference voltage ripple due to switching in SAR ADC introduces dynamic error which manifests as spurs in the output s pectrum and lim...\n\n\nDebnath Maiti, Sumukh Bhanushali, and Arindam Sany al (Arizona State University)\n---------------------\nLate Breaking Result s: Fast System Technology Co-Optimization Framework for Emerging Technolog y Based on Graph Neural Networks\n\nThis paper proposes a fast system tech nology co-optimization (STCO) framework that optimizes power, performance, and area (PPA) for next-generation IC design, addressing the challenges a nd opportunities presented by novel materials and device architectures. We focus on accelerating the technology le...\n\n\nTianliang Ma, Guangxi Fan , Xuguang Sun, Zhihui Deng, Kain Lu Low, and Leilai Shao (Shanghai Jiao To ng University)\n---------------------\nLate Breaking Results: Coulomb Forc e-Based Routability-Driven Placement Considering Global and Local Congesti on\n\nPlacement is a critical stage for VLSI routability optimization. A p lacement engine without considering the layout congestion might lead to po or solutions with routing failures. This paper introduces a Coulomb force- based global placement framework that addresses global and local routing c ongestions...\n\n\nJihai Meng and Shaohong Weng (Fuzhou University), Zhiji e Cai (Fudan University), Yilu Chen and Zhifeng Lin (Fuzhou University), a nd Jianli Chen (Fudan University)\n---------------------\nLate Breaking Re sults: Power Rail Routing for Advanced Multi-Layered Printed Circuit Board s\n\nThis paper proposes a power rail routing flow for advanced multi-laye red printed circuit boards (PCBs) to optimize segment area and via usage w hile satisfying IR drop requirements. With increasing current/voltage dema nds in modern PCBs, ultra-wide power rails may consume most routing space and cause...\n\n\nWei-Che Tseng, Zong-Ying Cai, Yu-Ping Huang, Yu-Hsiang L o, and Yao-Wen Chang (National Taiwan University)\n---------------------\n Late Breaking Results: Wiring Reduction for Field-coupled Nanotechnologies \n\nThe emergence of Field-coupled Nanocomputing (FCN) as a green and atom ically-sized post-CMOS technology introduces a unique challenge for the de velopment of physical design methods: unlike conventional computing, wire segments in FCN entail the same area and delay costs as standard gates. He nce, it ...\n\n\nSimon Hofmann, Marcel Walter, and Robert Wille (Technical University of Munich)\n---------------------\nLate Breaking Results: Lang uage-level QoR modeling for High-Level Synthesis\n\nThis paper proposes a language-level modeling approach for HLS based on the state-of-the-art Tra nsformer architecture. Our approach estimates the performance and resource requirements of HLS applications directly from the source code when diffe rent synthesis directives, in terms of HLS directives, a...\n\n\nDimosthen is Masouros and Aggelos Ferikoglou (National Technical University of Athen s), Georgios Zervakis (University of Patras), and Sotirios Xydia and Dimit rios Soudris (National Technical University of Athens) END:VEVENT END:VCALENDAR