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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20240626T180000
DTEND;TZID=America/Los_Angeles:20240626T190000
UID:dac_DAC 2024_sess256_LBR107@linklings.com
SUMMARY:Late Breaking Results: Machine Learning  Based Reference Ripple Er
 ror Suppression in Successive Approximation Register Analog-to-Digital Con
 verters
DESCRIPTION:Late Breaking Results Poster\n\nDebnath Maiti, Sumukh Bhanusha
 li, and Arindam Sanyal (Arizona State University)\n\nThis work presents a 
 machine learning (ML) technique to suppress reference ripple errors in suc
 cessive approximation register (SAR) analog-to-digital converter (ADC). Re
 ference voltage ripple due to switching in SAR ADC introduces dynamic erro
 r which manifests as spurs in the output spectrum and limits ADC resolutio
 n. Conventional techniques to suppress reference ripple require large deco
 upling capacitor and high-speed reference voltage buffer which consume lar
 ge area and power. The proposed ML approach uses a supervised technique in
  which a low-speed 10MHz SAR ADC is used for learning and correcting refer
 ence ripple error in a 200MHz SAR ADC. Simulated in 28nm CMOS technology, 
 the proposed ML approach reduces overall ADC power consumption by 4.9x wit
 hout degrading performance.
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