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DTSTAMP:20240626T180035Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20240626T180000
DTEND;TZID=America/Los_Angeles:20240626T190000
UID:dac_DAC 2024_sess256_LBR108@linklings.com
SUMMARY:Late Breaking Results: Power Rail Routing for Advanced Multi-Layer
 ed Printed Circuit Boards
DESCRIPTION:Late Breaking Results Poster\n\nWei-Che Tseng, Zong-Ying Cai, 
 Yu-Ping Huang, Yu-Hsiang Lo, and Yao-Wen Chang (National Taiwan University
 )\n\nThis paper proposes a power rail routing flow for advanced multi-laye
 red printed circuit boards (PCBs) to optimize segment area and via usage w
 hile satisfying IR drop requirements. With increasing current/voltage dema
 nds in modern PCBs, ultra-wide power rails may consume most routing space 
 and cause significant routing problems. We present an effective overlap-aw
 are rail sizing technique to distribute routing spaces appropriately accor
 ding to current/voltage demands and a resistance-aware A*-search algorithm
  to resolve overlapping regions by rail detouring.  Experimental results s
 how that our work significantly outperforms the state-of-the-art rail rout
 er in the metal area and runtime, achieving respective reductions of 49\% 
 and 28\%, without any current/voltage violations.
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